The invention relates in general to electronic circuit testing and more particularly to an apparatus utilizing data compression techniques.
Electronic circuits have become more and more complex and appropriate circuit testers need more and more functionality in order to be able to perform a sufficient test.
As the electronic circuits to be tested comprise a huge amount of electrical connections, such as pins, the equipment needed for the functional test of an electronic circuit increases significantly. Furthermore, there is a need to modify the test patterns to be applied to the electrical connections of an electronic circuit under test or to a board with several integrated circuits to be tested.
An electronic circuit or board tester should be easily adaptable for the test of various electronic circuits or boards having different numbers of electrical connections and functionality. Test parameters should be easily programmable. Each device under test (DUT) comprises several input and output electrical connections, such as pins. An electronic circuit or board tester applies digital signal patterns to the electrical connections of the DUT taking the specifications of the respective DUT into account. Digital output signals or digital patterns generated by the DUT are compared with a signal pattern of the same DUT having full functionality.
A DUT may be a memory circuit or a board with several memory circuits, such as RAMs, SRAMs, VRAMs, pipelined burst SRAMs etc. Each cell or at least most of the memorizing cells of the memory circuit have to be addressed, the binary signals "0" or "1" are written into each tested cell and it is checked, whether the contents of the cells are lost or modified, when accessing other cells of the memory circuit.
In order to carry out such memory tests, industry has developed several standard-test-patterns, such as "march, checkerboard, galpat etc.", addressing the cells in a specific chronical order.
Such standard-test-patterns make use of (for-next) loops and are used for the test of electronic memories and other electronic circuits.
Particularly, electronic circuit or board testers comprising individual tester circuits for each pin of the electronic device under test (DUT) are equipped with a large quantity of electronic memories such as expensive RAMs. Thus there is a need to reduce the amount of memories and/or memory capacity needed for carrying out a functionality test on various electronic circuits or boards, such as those comprising integrated circuits (ICs).
From U.S. Pat. No. 5,402,427 of the applicant, it is known to use a set of vector storage units each storing a segment of a test vector. In case that one test vector comprises two or more identical segments, this segment is stored only once. If for example the test data-segment at pin 1 and pin 2 are the same at the same clock cycle, this segment is stored only once. Furthermore, U.S. Pat. No. 5,402,427 proposes to use several sequences. It will be understood that a combination of a vector storage unit and an associated sequencer, each combination working independently except with regard to the same clock signal, cannot be used. Otherwise identical segments would have to be stored in more than one vector storage unit each being associated with a different electrical connection or pin of the DUT.
When using a modular circuit or board tester with a vector storage unit and an associated sequencer per electrical connection or pin of the DUT, there is a need for an electronic circuit or board tester having another concept.